Parallel-in, Serial-out Shift Register

Electrical Engineering
, , ,
1

Design a circuit that performs a bit shift operation on a multi-bit input (din) and outputs the shifted bits one at a time to a single-bit output (dout). The shifting should commence when the input enable signal (din_en) goes high, regardless of previous shifts. If all bits have been shifted, the output should be 0. Activate the reset (resetn) to treat the input value as 0. The input value remains 0 until the input enable signal triggers the shifting operation again.

2

Solution

Verilog

module model #(parameter DATA_WIDTH = 16) (
  input clk,          // Clock input
  input resetn,       // Active-low reset input
  input [DATA_WIDTH-1:0] din,    // Input data
  input din_en,       // Input enable signal
  output logic dout   // Output data
);

    logic [DATA_WIDTH-1:0] temp;  // Temporary variable for shifting

    always @(posedge clk) begin
        if (!resetn) begin  // Reset is active
            temp <= 0;     // Set temporary variable to 0
        end else if (din_en) begin  // Input enable signal is high
            temp <= din;   // Start shifting by assigning input to temporary variable
        end else begin
            temp <= temp >> 1;  // Shift temporary variable to the right by 1 bit
        end
    end

    assign dout = temp[0];  // Assign the least significant bit of the temporary variable to the output

endmodule